The present invention is generally applicable to any system in which data is driven down one or more communications channels. One example of such a system is a test system for testing electronic devices, such as semiconductor devices. FIG. 1 illustrates a simplified block diagram of a test system 100 for testing electronic devices. The test system 100 of FIG. 1 may test the dies of an unsingulated semiconductor wafer, singulated dies (packaged or unpackaged), or multi-chip modules. Such a system 100 may be configured to test other types of electronic devices, such as printed circuit boards, as well. As shown, the system 100 includes a tester 102, communications connection 104 (e.g., a coaxial cable, fiber optic link, wireless communications link, etc.), probe head 107, and a probe card 108 for communicating test signals between the tester 102 and the electronic device 112 under test (“DUT”). The test system 100 also includes a housing 106 with a moveable chuck 114 for supporting and moving the DUT 112. Probes 110 of the probe card make contact with the DUT 112 and thereby form electrical connections with the DUT.
The tester 102 generates test data, which is driven through communications channels comprising electrically conductive paths through communications connection 104, probe head 107, and probe card 108 to the input terminals (not shown in FIG. 1) of the DUT 112. Response data generated by the DUT 112 are output through output terminals of the DUT and travel to the tester 102 through compare channels (also comprising electrically conductive paths, through the probe card 108, probe head 108, and communications connection 104). Typically, the tester 102 then compares the response data generated by the DUT 112 to expected response data to determine whether the DUT 112 is good or bad. (Such testing may additionally or alternatively be used to rate operation of the DUT.)
FIG. 2 illustrates an exemplary DUT 112 with two input terminals 208 and 210, two output terminals 204 and 206, one power terminal 212, and one ground terminal 202. (A typical DUT may have many more terminals, but six terminals are shown in FIG. 2 for ease of illustration and discussion.) As shown in FIG. 2, power is provided from tester 102 to power terminal 212 through a power channel 224, which comprises electrically conductive paths through communications connection 104, probe head 107, and probe card 108, which includes probe 110f that contacts power terminal 212. A ground connection is similarly provided from tester 102 through ground channel 214, which terminates in probe 110a. Drivers 228 and 230 in tester 102 drive test data through drive channels 222 and 224, which terminate respectively in probes 110d and 110e, to input terminals 208 and 210. Response data generated by DUT 112 and output via output terminals 204 and 206 are received by comparators 232 and 234 in tester 102. (Comparators 232 and 234 may compare the response data with expected response data.) Control module 226 controls overall operation of the tester 102, provides power and ground, generates test data, acquires the results of comparing the actual response data with the expected response data, and/or generates timing signals, among other things.
FIG. 3 illustrates a partial view of tester 102, showing only drivers 228 and 230, which drive channels 222 and 220. In FIG. 3, resistor 308 represents the output impedance of a driver (228 or 230), and resistor 310 represents the characteristic impedance of a communications channel (220 or 222). In FIG. 3, it is assumed that DUT 112 is a complementary-metal-oxide-semiconductor (CMOS) device. As is known, an input terminal (e.g., 208 or 210) of a CMOS device (e.g., 112) is primarily capacitive. A simplified equivalent circuit for input terminals 208 and 210 is shown in FIG. 3 as a resistor 302 (representing an input resistance of an input terminal (e.g., 208 or 210)) in series with a capacitor 304 (representing the primarily capacitive nature of the input terminals 208 and 210). (306 represents ground.)
As is known, a change from a low to a high signal at an input terminal 208 or 210 does not register in DUT 112 until a sufficient charge builds up on capacitor 304. Similarly, a change from a high to a low signal at an input terminal 208 or 210 does not register in DUT 112 until the charge on capacitor 304 dissipates. The time needed to charge capacitor 304 is often referred to as rise time, and the time needed to discharge capacitor 304 is fall time.
As is known, the rise time of a resistor and a capacitor in series is proportional to the product of the resistance and capacitance. The time constant (τ) of the rise time is as follows: τ=R*C (where τ is the time constant of the rise time or the fall time, R is the resistance of the resistor, C is the capacitance of the capacitor, and * refers to multiplication). The voltage across the capacitor 304 is as follows: vc(t)=C*vd*(1−e−t/τ) where:                vc(t) is the voltage across capacitor 304 at time t,        vd is the output voltage of driver 228 or 230,        t is the time from the rising edge of vd (from a low to a high voltage level),        τ is the time constant, and τ=R*C,        R is the total resistance between each driver 228 and 230 and the capacitance 304 of each input terminal 208 and 210 (R is thus the sum of the output impedance 308 of a driver, the characteristic impedance 310 of a drive channel, and the input resistance 302 of an input terminal of DUT 112), and        C is the capacitance of capacitor 304.        
The fall time of a resistor and capacitor in series is also proportional to the product of the resistance and the capacitance, and the same time constant (τ) is applicable. The voltage across the capacitor 304 is as follows: vc(t)=C*vo*e−t/τ where vo is the initial charge on the capacitor and the other parameters are as defined above.
As should be apparent, the rise time and fall time of the input terminals 208 and 210 limit the frequency at which input signals to DUT 112 may be switched. As should also be apparent, the test system 100 may add to the rise and fall times of the input terminals 208 and 210 of DUT 112. This is because, for each driver 228 and 230 and drive channel 220 and 222, the output impedance 308 of the driver 228 and 230 and the characteristic impedance 310 of the channels 220 and 222 effectively increase the input resistance 302 of the input terminals 208 and 210 of DUT 112.
Another potential limit on the frequency at which DUT 112 may be switched arises from signal reflections on channels 220 and 222. A test signal driven by driver 228 or 230 down channel 222 or 220 will reflect (at least partially) off of input terminal 210 or 208 and travel back up the channel 222 or 220 toward the driver 228 or 230. If the driver output impedance 308 matches the characteristic impedance 310 of the channel (222 or 220), the reflected signal is absorbed by the driver output impedance 308 and is not further reflected back down the channel (222 or 220) toward the DUT 112. Such a configuration in which the output impedance of the driver (or source of the signal) matches the characteristic impedance of the channel is often referred to as “source termination.” Even if the system shown in FIG. 3 is source terminated, the reflections that travel back up the channels 222 and 220 may cause jitter, noise, or inter-symbol interference that limits the frequency at which the input terminals 210 and 208 may be switched.
In many test applications, it would be advantageous to increase the frequency at which a DUT may be tested.